Associated with the rapid progress of semiconductor integration circuit techniques and the development of a higher integration of semiconductor elements, a technological revolution for a semiconductor memory devices has been in progress with the aim of gaining larger capacity and further miniaturization.
One recent problem accompanying a large capacity flash memory (on the order of gigabytes) is the extension of the length of bit lines. This causes the resistance value R of the bit line to increase and the parasitic capacity C between the bit lines to increase, thus increasing a time constant RC of the bit lines. An increase in the time constant RC results in increasing the time period required for sense amplifiers connected to the bit lines to sense voltages on the bit lines corresponding to read data and apply voltages to the bit lines corresponding to write data.
A data read operation performed in common flash memory device requires pre-charging of the bit lines. The reason is that, to confirm whether a memory cell is in an erase state “1” or program state “0”, a verification of a change in potential is difficult unless the bit line is provided with a certain level of potential. A common practice is to apply a pre-charging voltage to increase the voltage of the bit line to a predetermined value in advance, followed by detecting a change in the voltage of the bit line when the bit line is applied to a memory cell by comparing the voltage of the bit line with the pre-charged voltage used as a reference. The pre-charging is performed without exception for both a read operation and a verification operation, i.e., performing a read operation to confirm that a memory cell has been properly programmed. Therefore, the time required for pre-charging has a large influence on data access time.
The problem of increased time constant RC of bit lines resulting from higher capacities can be solved to some extent by fabricating the bit lines from a low resistance material, thereby decreasing the resistance of the bit lines. However, doing so can greatly increase the cost of such memory device, thus making this approach generally unsuitable.
Another approach to solving this problem that has been proposed is to divide the memory cell array into two parts, thereby reducing the lengths of the bit lines in each array. With reference to FIG. 1, a flash memory cell array unit 101 is divided into two parts 102 and 104, and a data register unit 103 is between the memory cell arrays 102 and 104. This configuration reduces both the resistance R and parasitic capacity C of the bit line 107 to approximately half the values they would have if the array unit 101 was not divided. As a result, the time constant RC of the bit lines, which is the product of the two, is reduced to an approximately quarter of the value the time constant would be if the array unit 101 was not divided. Therefore, the array unit 101 can be accessed about four times faster.
The configuration of placing the data register unit 103 between the memory cell arrays 102 and 104 constitutes an effective method for decreasing the time constant that is the product of the resistance and parasitic capacity of a bit line and for shortening the access time. A few problems are left unsolved, however. First, placing the data register unit 103 between the arrays 102, 104 inherently positions it farther away from the state machine 105 and hence farther from the input/output pads 106. As a result, the times required for signals to be coupled between the data register unit 103 and both the state machine 105 and the input/output pads 106 can be greatly increased. This results in increasing the access time to obtain data from the bit lines. In view of the fact that the read cycle time has been shortened to levels like 50 nanoseconds in recent years, these increased access times can pose a large problem.
Another problem with placing the data register unit 103 between the memory cell arrays 102 and 104 is that doing so requires that a large number of signal lines 108 extend through the array unit 101 at one side of the array 104. The area of the array unit 101 required to accommodate all of these signal lines can greatly increase the width of the array unit 101. As a result, less surface area of the array unlit 101 is available for the array 104, which can limit the capacity of the array unit 101 and increase the cost of a memory device containing the array unit 101. There is therefore a need for an improved memory array unit and method that results in a large data storage capacity, a high operating speed and efficient use of semiconductor substrates on which memory devices are fabricated.